The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to vertical field effect transistors (VFETs) with self-aligned contacts.
Field effect transistors (FETs) have been known for a number of years and are now the transistor of choice for use in complex integrated digital circuits. In general, field effect transistors can be fabricated somewhat more simply and with larger process windows than bipolar transistors and, additionally, allow simplified circuit and device design. As demands for higher digital switching performance have increased, as well as demands for increased functionality and economy of manufacture, constraints on transistor footprint size (and, hence, current-carrying capacity) have also increased.
Traditional CMOS (complementary metal oxide semiconductor) fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to nonplanar transistor architectures. Some non-planar transistor architectures, such as VFETs, employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VFETs the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin or nanowire extends upward from the substrate surface. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.
Decoupling the gate length from the gate pitch greatly improves the scaling of transistor density. With VFETs device scaling is determined by how closely conductive via contacts can be placed to source/drain and gate regions of the transistor. Unlike planar transistors, however, where self-aligned contact processes (which determine the spacing between source/drain contacts and a gate electrode) can be used, there are no known techniques for forming self-aligned contacts for VFETs. Consequently, the bottom source/drain contact-to-fin and gate contact-to-fin spacing requirements have not scaled at the same rate as other VFET features. These spacing requirements represent an area penalty that severely restricts the overall scaling factor of the VFET architecture. Reducing this area penalty and improving the scaling of these aspects of the VFET architecture is critical to achieve an overall scaling factor sufficient to enable sub-5 nm VFETs.